The demand for high-speed wireless communication systems has grown signif-
icantly in recent years. Millimeter-wave (mmWave) frequencies, especially the
60 GHz band, offer ample bandwidth for the demand. Simultaneously, integrating
communication and sensing capabilities on a single platform has become a focus
to increase the versatility and capability of modern RF front-ends. This integra-
tion optimizes hardware resources and fosters efficient wireless systems. While
technologies like Silicon Germanium (SiGe) have been traditionally used for high-
frequency RF front-ends, CMOS technology has gained prominence because of
its unique advantages. CMOS offers superior integration capabilities with digital
circuits, enabling energy-efficient systems with both communication and sensing
functionalities on a single chip.
This thesis delves into cutting-edge mmWave RF front-end circuit design in a
22 nm FDSOI technology, particularly focused on 60 GHz applications and joint
sensing and communication systems. Divided into two major parts, the thesis
showcases significant advancements in circuit design efficiency and system inte-
gration.
The initial segment of the thesis is dedicated to the exploration of power am-
plifiers (PAs) operating at 60 GHz. A new operation class J/F which combines
the benefit of both classes J and F is proposed. The J/F class revolutionizes PA
efficiency by elongating the voltage swing by harnessing the second harmonic and
refining the voltage and current waveforms via the third harmonic. To prove the
concept of this theoretical framework, a 60 GHz PA was fabricated using the 22 nm
FDSOI technology. Notably, this PA achieved a record-breaking Power Added Ef-
ficiency (PAE) of 42.3% while occupying a remarkably reduced active area. These
accomplishments underscore the thesis’s overarching goal of enhancing key perfor-
mance metrics for power amplifiers, thereby addressing the demands of mmWave
applications.
The second half of the thesis addresses low-power frequency synthesis at 30 GHz,
incorporating a fractional-N synthesizer with dual charge pumps and a class D
VCO which set the new record of Figure of Merit (FOM) among VCOs using the
same 22 nm FDSOI technologies. The phase locked loop (PLL), with only 16 mW
DC power, achieves comparable frequency chirp speed and RMS frequency error
to the state-of-the-art PLLs with much higher consumption. In addition to its
low power consumption, the proposed fractional-N PLL features a hybrid design,
wherein the digital control circuits and sigma delta modulator (SDM) are imple
mented in an FPGA, while other circuit components are integrated into a 22 nm
chip. This hybrid architecture endows the PLL with exceptional flexibility, allow-
ing seamless switching between different SDMs and control logic configurations.
Also, this hybrid method makes it possible to utilize distinct semiconductor tech-
nologies to implement ultra-fast mmWave circuits and their corresponding logic
circuits, leveraging the strengths of each technology. However, this approach in-
troduces inherent additional delays between the SDM and frequency dividers,
which may potentially disrupt the PLL’s operation. This phenomenon is thor-
oughly studied in this thesis and a general solution is derived based on theoretical
analysis.
In both communication and Frequency Modulated Continuous Wave (FMCW)
radar systems, minimizing phase and amplitude errors in the local oscillator (LO)
signal is critical for maintaining signal integrity, achieving accurate measurements,
and ensuring reliable system operation. To ensure precise quadrature output at
60 GHz a novel super harmonic injection-locked oscillator (ILO) method is in-
troduced, leveraging a unique phase accuracy mechanism based on a Marchand
balun working the at second harmonic frequency. To prove the concept of the
theoretical analysis, a super harmonic injection-locked oscillator (ILO) fabricated
using the 22 nm FDSOI technology is proposed and characterized in the labora-
tory. This oscillator facilitates the generation of highly precise quadrature outputs
with minimal phase and amplitude errors across its locking range.
By emphasizing the exceptional PAE achievement, the innovative working prin-
ciple of the super harmonic ILO, and the effective resolution of PLL synchroniza-
tion challenges, this thesis contributes significantly to advancing mmWave RF
front-end circuit design, setting the stage for enhanced joint sensing and commu-
nication systems in the future.